Return Registers And Instructions - Analog Devices ADSP-BF53x Blackfin Reference

Events and Interrupts
Table 4-8 lists events by priority. Each event has a corresponding bit in
the event state registers
Table 4-8. Core Event Vector Table
Name Event Class
EMU Emulation
RST Reset
NMI NMI
EVX Exception
Reserved Reserved
IVHW Hardware Error
IVTMR Core Timer
IVG7 Interrupt 7
IVG8 Interrupt 8
IVG9 Interrupt 9
IVG10 Interrupt 10
IVG11 Interrupt 11
IVG12 Interrupt 12
IVG13 Interrupt 13
IVG14 Interrupt 14
IVG15 Interrupt 15

Return Registers and Instructions

Similarly to the
interrupts and exceptions also use single-entry hardware stack registers. If
an interrupt is serviced, the program sequencer saves the return address
4-42 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
,
ILAT IMASK
Event Vector
Register
EVT0
EVT1
EVT2
EVT3
EVT4
EVT5
EVT6
EVT7
EVT8
EVT9
EVT10
EVT11
EVT12
EVT13
EVT14
EVT15
register controlled by
RETS
, and .
IPEND
MMR Location
0xFFE0 2000
0xFFE0 2004
0xFFE0 2008
0xFFE0 200C
0xFFE0 2010
0xFFE0 2014
0xFFE0 2018
0xFFE0 201C
0xFFE0 2020
0xFFE0 2024
0xFFE0 2028
0xFFE0 202C
0xFFE0 2030
0xFFE0 2034
0xFFE0 2038
0xFFE0 203C
and
CALL RTS
Notes
Highest priority. Vec-
tor address is provided
by JTAG.
Reserved vector
System interrupt
System interrupt
System interrupt
System interrupt
System interrupt
System interrupt
System interrupt
System interrupt
Software interrupt
instructions,