Analog Devices ADSP-BF53x Blackfin Reference page 580

Instruction Overview
: Optionally
opt_mode
be used with MAC1 versions either alone or with any of these other
options. If multiple options are specified together for a MAC, the options
must be separated by commas and enclosed within a single set of parenthe-
sis. Example:
(M, IS)
Instruction Length
In the syntax, comment (b) identifies 32-bit instruction length.
Functional Description
This instruction multiplies two 16-bit half-word operands. The instruc-
tion stores, adds or subtracts the product into a designated Accumulator.
It then copies 32 bits of the Accumulator into a data register. The 32 bits
are saturated at 32 bits.
The Multiply-and-Accumulate Unit 0 (MAC0) portion of the architecture
performs operations that involve Accumulator
an even-numbered data register. MAC1 performs
the results into an odd-numbered data register.
Combinations of these instructions can be combined into a single instruc-
tion. See "Vector Multiply and Multiply-Accumulate" on page
Options
The Multiply and Multiply-Accumulate to Data Register instruction sup-
ports operand and Accumulator copy options.
These options are as shown in
The syntax supports only biased rounding. The
register has no bearing on the rounding behavior of this instruction.
See "Rounding and Truncating" on page 1-19
ing behavior.
15-68 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
, ,
(FU) (IS) (S2RND)
Table 15-5.
, or . Optionally,
(ISS2)
; it loads the results into
A0
operations and loads
A1
bit in the
RND_MOD
for a description of round-
can
(M)
19-41.
ASTAT