Test And Set Byte (Atomic) - Analog Devices ADSP-BF53x Blackfin Reference

Instruction Overview

Test and Set Byte (Atomic)

General Form
TESTSET
Syntax
TESTSET ( Preg ) ;
Syntax Terminology
: (
Preg P5–0 SP
Instruction Length
In the syntax, comment (a) identifies 16-bit instruction length.
Functional Description
The Test and Set Byte (Atomic) instruction loads an indirectly addressed
memory byte, tests whether it is zero, then sets the most significant bit of
the memory byte without affecting any other bits. If the byte is originally
zero, the instruction sets the
instruction clears the
atomic.
accesses the entire logical memory space except the core Mem-
TESTSET
ory-Mapped Register (MMR) address region. The system design must
ensure atomicity for all memory regions that
hardware does not perform atomic access to L1 memory space configured
as SRAM. Therefore, semaphores must not reside in on-core memory.
The memory architecture always treats atomic operations as cache-inhib-
ited accesses, even if the
cache-enabled access. If a cache hit is detected, the operation flushes and
invalidates the line before allowing the
16-22 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
/* (a) */
and are not allowed as the register for this instruction)
FP
bit. If the byte is originally nonzero the
CC
bit. The sequence of this memory transaction is
CC
descriptor for the address indicates a
CPLB
may access. The
TESTSET
to proceed.
TESTSET