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Vector Operations Instructions
Table C-21. Vector Operations Instructions (Sheet 14 of 33)
Instruction
and Version
Vector Multiply
Dreg_even = Dreg_lo_hi * Dreg_lo_hi ,
Dreg_odd = Dreg_lo_hi * Dreg_lo_hi (IS, M)
Vector Multiply
Dreg_even = Dreg_lo_hi * Dreg_lo_hi ,
Dreg_odd = Dreg_lo_hi * Dreg_lo_hi (S2RND, M)
Vector Multiply
NOTE: When issuing compatible load/store instructions in parallel with a Vector Multiply instruction,
add 0x0800 0000 to the Vector Multiply opcode.
NOTE: The ranges of these vector opcodes naturally overlaps with the component scalar Multiply 16-Bit
Operands opcodes. In fact, each vector opcode is the logical "OR" of the two component scalar opcodes.
Dreg_even = Dreg_lo_hi * Dreg_lo_hi ,
Dreg_odd = Dreg_lo_hi * Dreg_lo_hi (ISS2, M)
C-120
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Opcode
Range
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 0 0 0 1 1 0 0 0 1 1 1 0 0
0xC31C 2000—
0xC31C E7FF
Dreg
half 1 1 0 0
1 1 0 0 0 0 1 0 0 0 1 1 1 1 0 0
0xC239 2000—
0xC239 E7FF
Dreg
half 1 1 0 0
1 1 0 0 0 0 1 1 0 0 1 1 1 1 0 0
0xC33C 2000—
0xC33C E7FF
Dreg
half 1 1 0 0
Bin
Dreg
Dest.
src_reg_
half 0
Dreg #
0 Dreg #
Dreg
Dest.
src_reg_
half 0
Dreg #
0 Dreg #
Dreg
Dest.
src_reg_
half 0
Dreg #
0 Dreg #
src_reg_
1 Dreg #
src_reg_
1 Dreg #
src_reg_
1 Dreg #
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