Analog Devices ADSP-BF53x Blackfin Reference page 627

The software designer is responsible for executing atomic operations in the
proper cacheable / non-cacheable memory space. Typically, these opera-
tions should execute in non-cacheable, off-core memory. In a chip
implementation that requires tight temporal coupling between processors
or processes, the design should implement a dedicated, non-cacheable
block of memory that meets the data latency requirements of the system.
can be interrupted before the load portion of the instruction
TESTSET
completes. If interrupted, the
from the interrupt. After the test or load portion of the
pletes, the
TESTSET
exceptions associated with the
operations must be completed before the load of the
The integrity of the
resource-locking mechanism. If the L2 memory does not support atomic
locking for the address region you are accessing, your software has no
guarantee of correct semaphore behavior. See the processor L2 memory
documentation for more on the locking support.
Flags Affected
This instruction affects flags as follows.
• is set if addressed value is zero; cleared if nonzero.
CC
• All other flags are unaffected.
The ADSP-BF535 processor has fewer
operate differently than subsequent Blackfin family products. For
more information on the ADSP-BF535 status flags, see
on page
Required Mode
User & Supervisor
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
TESTSET
sequence cannot be interrupted. For example, any
CPLB
atomicity depends on the L2 memory
TESTSET
A-3.
External Event Management
will be re-executed upon return
lookup for both the load and store
TESTSET
flags and some flags
ASTAT
com-
TESTSET
completes.
Table A-1
16-23