Data Cache Invalidation; Data Test Registers - Analog Devices ADSP-BF53x Blackfin Reference

Data Test Registers

Data Cache Invalidation

Besides the
FLUSHINV
additional methods are available to invalidate the data cache when flush-
ing is not required. The first technique directly invalidates Valid bits by
setting the Invalid bit of each cache line to the invalid state. To implement
this technique, additional MMRs (
are available to allow arbitrary reads/writes of all the cache entries directly.
This method is explained in the next section.
For invalidating the complete data cache, a second method is available. By
clearing the
DMC[1:0]
"L1 Data Memory Control Register," on page
data cache are set to the invalid state. A second write to the
register to set the
data memory back to its previous cache/SRAM configuration. An
instruction should be run before invalidating the cache and a
instruction should be inserted after each of these operations.
Data Test Registers
Like L1 Instruction Memory, L1 Data Memory contains additional
MMRs to allow arbitrary reads/writes of all cache entries directly. The reg-
isters provide a mechanism for data cache test, initialization, and debug.
When the Data Test Command register (
L1 cache data or tag arrays are accessed and data is transferred through the
Data Test Data registers (
ters contain the 64-bit data to be written, or they contain the destination
for the 64-bit data read. The lower 32 bits are stored in the
register and the upper 32 bits are stored in the
When the tag arrays are being accessed, then the
used.
A
CSYNC
MMR.
6-38 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
instruction, explained in the previous section, two
bits in the
DMEM_CONTROL
bits to their previous state then configures the
DMC[1:0]
DTEST_DATA[1:0]
instruction is required after writing the
and
DTEST_COMMAND
register (see
6-25), all Valid bits in the
DTEST_COMMAND
). The
DTEST_DATA[1:0]
DTEST_DATA[1]
DTEST_DATA[0
)
DTEST_DATA[1:0]
Figure 6-9,
DMEM_CONTROL
SSYNC
CSYNC
) is written to, the
regis-
DTEST_DATA[0]
register.
] register is
DTEST_COMMAND