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ICPLB_DATAx Registers
Figure 6-19
describes the ICPLB Data registers (
To ensure proper behavior and future compatibility, all reserved
bits in this register must be set to 0 whenever this register is
written.
ICPLB Data Registers (ICPLB_DATAx)
For Memory-
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
mapped
addresses, see
Table
6-2.
15 14 13 12 11 10
CPLB_L1_CHBL
Clear this bit whenever L1 memory
is configured as SRAM
0 - Non-cacheable in L1
1 - Cacheable in L1
CPLB_LRUPRIO
See
"Instruction Cache Locking by Line" on page 6-16
0 - Low importance
1 - High importance
Figure 6-19. ICPLB Data Registers
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
0
0
0
0
0
0
0
0
9
8
0
0
0
0
0
0
0
0
ICPLB_DATAx
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Memory
).
Reset = 0x0000 0000
PAGE_SIZE[1:0]
00 - 1K byte page size
01 - 4K byte page size
10 - 1M byte page size
11 - 4M byte page size
CPLB_VALID
0 - Invalid (disabled) CPLB
entry
1 - Valid (enabled) CPLB
entry
CPLB_LOCK
Can be used by software in
CPLB replacement algorithms
0 - Unlocked, CPLB entry can
be replaced
1 - Locked, CPLB entry
should not be replaced
CPLB_USER_RD
0 - User mode read access
generates protection
violation exception
1 - User mode read access
permitted
6-55
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