Analog Devices ADSP-BF53x Blackfin Reference page 922

Vector Operations Instructions
Table C-21. Vector Operations Instructions (Sheet 16 of 33)
Instruction
and Version
Vector Multiply and
Multiply-Accumulate
A0 {=, +=, or –=} Dreg_lo_hi * Dreg_lo_hi ,
A1 {=, +=, or –=} Dreg_lo_hi * Dreg_lo_hi (FU)
Vector Multiply and
Multiply-Accumulate
A0 {=, +=, or –=} Dreg_lo_hi * Dreg_lo_hi ,
A1 {=, +=, or –=} Dreg_lo_hi * Dreg_lo_hi (IS)
Vector Multiply and
Multiply-Accumulate
A0 {=, +=, or –=} Dreg_lo_hi * Dreg_lo_hi ,
A1 {=, +=, or –=} Dreg_lo_hi * Dreg_lo_hi (W32)
Vector Multiply and
Multiply-Accumulate
A0 {=, +=, or –=} Dreg_lo_hi * Dreg_lo_hi ,
A1 {=, +=, or –=} Dreg_lo_hi * Dreg_lo_hi (M)
Vector Multiply and
Multiply-Accumulate
NOTE: When issuing compatible load/store instructions in parallel with a Vector Multiply and Multi-
ply-Accumulate instruction, add 0x0800 0000 to the Vector Multiply and Multiply-Accumulate opcode.
NOTE: The ranges of these vector opcodes naturally overlaps with the component scalar Multiply and
Multiply-Accumulate opcodes. In fact, each vector opcode is the logical "OR" of the two component sca-
lar opcodes.
A0 {=, +=, or –=} Dreg_lo_hi * Dreg_lo_hi ,
A1 {=, +=, or –=} Dreg_lo_hi * Dreg_lo_hi (W32, M)
C-122 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Opcode
Range 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 0 0 0 0 0 1 0 0 0 0 0 op1
0xC080 0000—
0xC083 DE3F Dreg
half 1 0 op0
1 1 0 0 0 0 0 1 0 0 0 0 0 0 op1
0xC100 0000—
0xC103 DE3F Dreg
half 1 0 op0
1 1 0 0 0 0 0 0 0 1 1 0 0 0 op1
0xC060 0000—
0xC063 DE3F Dreg
half 1 0 op0
1 1 0 0 0 0 0 0 0 0 0 1 0 0 op1
0xC010 0000—
0xC013 DE3F Dreg
half 1 0 op0
1 1 0 0 0 0 0 0 0 1 1 1 0 0 op1
0xC070 0000—
0xC073 DE3F Dreg
half 1 0 op0
Bin
Dreg src_reg_
half 0 0 0 0 0 Dreg #
Dreg src_reg_
half 0 0 0 0 0 Dreg #
Dreg src_reg_
half 0 0 0 0 0 Dreg #
Dreg src_reg_
half 0 0 0 0 0 Dreg #
Dreg src_reg_
half 0 0 0 0 0 Dreg #
src_reg_
1 Dreg #
src_reg_
1 Dreg #
src_reg_
1 Dreg #
src_reg_
1 Dreg #
src_reg_
1 Dreg #