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Arithmetic Operations Instructions
Table C-17. Arithmetic Operations Instructions (Sheet 14 of 44)
Instruction
and Version
Multiply 16-Bit Operands
Dreg_odd = Dreg_lo_hi * Dreg_lo_hi (FU, M)
Multiply 16-Bit Operands
Dreg_odd = Dreg_lo_hi * Dreg_lo_hi (IS, M)
Multiply 16-Bit Operands
Dreg_odd = Dreg_lo_hi * Dreg_lo_hi (S2RND, M)
Multiply 16-Bit Operands
NOTE: When issuing compatible load/store instructions in parallel with a Multiply 16-Bit Operands
instruction, add 0x0800 0000 to the Multiply 16-Bit Operands opcode.
Dreg_odd = Dreg_lo_hi * Dreg_lo_hi (ISS2, M)
Multiply 32-Bit Operands
Dreg *= Dreg
C-68
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Opcode Range
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0xC29C 0000—
1 1 0 0 0 0 1 0 1 0 0 1 1 1 0 0
0xC29C C1FF
Dreg
half
0xC31C 0000—
1 1 0 0 0 0 1 1 0 0 0 1 1 1 0 0
0xC31C C1FF
Dreg
half
0xC239 0000—
1 1 0 0 0 0 1 0 0 0 1 1 1 1 0 0
0xC239 C1FF
Dreg
half
0xC33C 0000—
1 1 0 0 0 0 1 1 0 0 1 1 1 1 0 0
0xC33C C1FF
Dreg
half
0x40C0—
0 1 0 0 0 0 0 0 1 1 Source
0x40FF
Bin
0 0 0 0 0 Dest.
Dreg #
0 0 0 0 0 Dest.
Dreg #
0 0 0 0 0 Dest.
Dreg #
0 0 0 0 0 Dest.
Dreg #
src_reg_
src_reg_
0 Dreg #
1 Dreg #
src_reg_
src_reg_
0 Dreg #
1 Dreg #
src_reg_
src_reg_
0 Dreg #
1 Dreg #
src_reg_
src_reg_
0 Dreg #
1 Dreg #
Dest.
Dreg #
Dreg #
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