Analog Devices ADSP-BF53x Blackfin Reference page 1030

Index
pointer registers (P[5:0])
description of, C-2
example, 5-3
indirect/post-increment index
addressing, 8-47
load half-word – sign-extended
instruction, 8-20
source pointer register,
user mode, 3-4
pop instruction, 10-8,
pop multiple instruction, 10-12,
popping, manual, 4-5
PORT_PREF0 (DAG0 port preference)
bit, 6-25, 6-26
PORT_PREF1 (DAG1 port preference)
bit, 6-24, 6-25
post-modify addressing
AAU architecture, 5-2
circular buffering, 5-13
defined, 5-5
example, 5-11
post-modify buffer access,
powerdown warning, as NMI,
powerup, 3-12
PRCENx bits, 21-20
PREFETCH (data cache prefetch)
instruction, 6-37, 17-3,
Preg. See pointer registers (P[5:0])
pre-modify instruction example,
pre-modify stack pointer addressing,
prioritization of events,
priority watermark (PRIO_MARK[0:3])
field, 6-36
processor, single-core bus architecture,
processor core architecture, diagram, 1-2,
2-2
processor mode
determination, 3-1
emulation, 3-9
I-28 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
(continued)
8-11
C-37
C-37
5-14
4-46
C-101
5-11
5-11
1-6
6-2
processor mode
figure, 3-2
identifying, 3-2
IPEND interrogation,
supervisor, 3-7
user, 3-3
processor state
idle, 3-9
reset, 3-10
upon reset, 3-11
product identification (DSPID) register.
See DSPID (product identification)
register
program counter (PC) register
non-memory mapped,
PC-relative indirect JUMP and CALL,
4-13
PC-relative offset, 4-11
program flow
control instructions,
controlling, 4-19
described, 4-1
instructions, 7-2
sequencer tasks for, 1-3
program sequencer, 4-1
history, 21-15
tasks performed, 1-3
program structures, nonsequential,
protected
instructions, 3-4
memory, 3-5
memory regions, 6-54
resources, 3-4
protected instructions,
protection violation exceptions, 17-3, 17-5,
17-7, 17-9
pushing, manual, 4-5
push instruction, 10-2,
push multiple instruction, 10-5,
(continued)
3-1
4-6
C-13
to 4-58
4-1
3-4
C-37
C-37