Analog Devices ADSP-BF53x Blackfin Reference page 142

Instruction Pipeline
Figure 4-3 shows a diagram of the pipeline.
Instr Instr
Fetch
Fetch
1 2
Instr Instr Instr
Fetch Fetch Fetch
1 2 3
Figure 4-3. Processor Pipeline
The instruction fetch and branch logic generates 32-bit fetch addresses for
the Instruction Memory Unit. The Instruction Alignment Unit returns
instructions and their width information at the end of the IF3 stage.
For each instruction type (16, 32, or 64 bits), the Instruction Alignment
Unit ensures that the alignment buffers have enough valid instructions to
be able to provide an instruction every cycle. Since the instructions can be
16, 32, or 64 bits wide, the Instruction Alignment Unit may not need to
fetch an instruction from the cache every cycle. For example, for a series of
16-bit instructions, the Instruction Alignment Unit gets an instruction
from the Instruction Memory Unit once in four cycles. The alignment
logic requests the next instruction address based on the status of the align-
ment buffers. The sequencer responds by generating the next fetch address
in the next cycle, provided there is no change of flow.
The sequencer holds the fetch address until it receives a request from the
alignment logic or until a change of flow occurs. The sequencer always
increments the previous fetch address by 8 (the next 8 bytes). If a change
of flow occurs, such as a branch or an interrupt, data in the Instruction
Alignment Unit is invalidated. The sequencer decodes and distributes
instruction data to the appropriate locations such as the register file and
data memory.
The Execution Unit contains two 16-bit multipliers, two 40-bit ALUs,
two 40-bit accumulators, one 40-bit shifter, a video unit (which adds 8-bit
ALU support), and an 8-entry 32-bit Data Register File.
4-8 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Instr Instr Addr
Decode Calc
Fetch
3
Instr Addr Data
Decode Calc Fetch
1
Data Data
Ex1
Fetch
Fetch
1 2
Data Ex1 Ex2
Fetch
2
Ex2
WB
WB