Special Rounding Instructions; Using Computational Status - Analog Devices ADSP-BF53x Blackfin Reference

Using Computational Status

Special Rounding Instructions

The ALU provides the ability to round the arithmetic results directly into
a data register with biased or unbiased rounding as described above. It also
provides the ability to round on different bit boundaries. The options
, , and
RND12 RND
regardless of the state of the
For example:
R3.L = R4 (RND) ;
performs biased rounding at bit 16, depositing the result in a half word.
R3.L = R4 + R5 (RND12) ;
performs an addition of two 32-bit numbers, biased rounding at bit 12,
depositing the result in a half word.
R3.L = R4 + R5 (RND20) ;
performs an addition of two 32-bit numbers, biased rounding at bit 20,
depositing the result in a half word.
Using Computational Status
The multiplier, ALU, and shifter update the overflow and other status
flags in the processor's Arithmetic Status (
conditions from computations in program sequencing, use conditional
instructions to test the
executes. This method permits monitoring each instruction's outcome.
The register is a 32-bit register, with some bits reserved. To ensure
ASTAT
compatibility with future implementations, writes to this register should
write back the values read from these reserved bits.
2-24 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
round at bit 12, bit 16, and bit 20, respectively,
RND20
RND_MOD
flag in the
CC
bit in .
ASTAT
) register. To use status
ASTAT
register after the instruction
ASTAT