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17 CACHE CONTROL
Instruction Summary
•
"PREFETCH" on page 17-3
•
"FLUSH" on page 17-5
•
"FLUSHINV" on page 17-7
•
"IFLUSH" on page 17-9
Instruction Overview
This chapter discusses the instructions that are used to flush, invalidate,
and prefetch data cache lines as well as the instruction used to invalidate a
line in the instruction cache.
As part of the data-cache related instructions, the
can be used to improve performance by initiating a data cache-line fill in
advance of when the desired data is actually required for processing. The
instruction is useful when data cache is configured in the write-back
FLUSH
mode (which is described in further detail in the
instruction forces data in the cache line that has been changed by the pro-
cessor (and thus has been marked as "dirty") to be written to its source
memory.
There is no single instruction that can be used to invalidate a data
cache-line. The
invalidate a data cache-line. The
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
instruction provides a way to directly flush and
FLUSHINV
"Memory"
instruction is commonly used
FLUSHINV
instruction
PREFETCH
chapter). This
17-1
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