Analog Devices ADSP-BF53x Blackfin Reference page 875

Table C-17. Arithmetic Operations Instructions (Sheet 21 of 44)
Instruction
and Version
Multiply and Multiply-Accumulate
to Half Register
Dreg_lo = (A0 = Dreg_lo_hi * Dreg_lo_hi) (IU)
Multiply and Multiply-Accumulate
to Half Register
Dreg_lo = (A0 = Dreg_lo_hi * Dreg_lo_hi) (T)
Multiply and Multiply-Accumulate
to Half Register
Dreg_lo = (A0 = Dreg_lo_hi * Dreg_lo_hi) (TFU)
Multiply and Multiply-Accumulate
to Half Register
Dreg_lo = (A0 = Dreg_lo_hi * Dreg_lo_hi) (S2RND)
Multiply and Multiply-Accumulate
to Half Register
Dreg_lo = (A0 = Dreg_lo_hi * Dreg_lo_hi) (ISS2)
Multiply and Multiply-Accumulate
to Half Register
NOTE: When issuing compatible load/store instructions in parallel with a Multiply and Multiply-Accumu-
late instruction, add 0x0800 0000 to the Multiply and Multiply-Accumulate opcode.
Dreg_lo = (A0 = Dreg_lo_hi * Dreg_lo_hi) (IH)
Multiply and Multiply-Accumulate
to Half Register
Dreg_lo = (A0 += Dreg_lo_hi * Dreg_lo_hi)
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Opcode Range 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0xC183 2000— 1 1 0 0 0 0 0 1 1 0 0 0 0 0 1 1
0xC183 27FF
0 0 1 0 0 Dreg
0xC043 2000— 1 1 0 0 0 0 0 0 0 1 0 0 0 0 1 1
0xC043 27FF
0 0 1 0 0 Dreg
0xC0C3 2000— 1 1 0 0 0 0 0 0 1 1 0 0 0 0 1 1
0xC0C3 27FF
0 0 1 0 0 Dreg
0xC023 2000— 1 1 0 0 0 0 0 0 0 0 1 0 0 0 1 1
0xC023 27FF
0 0 1 0 0 Dreg
0xC123 2000— 1 1 0 0 0 0 0 1 0 0 1 0 0 0 1 1
0xC123 27FF
0 0 1 0 0 Dreg
0xC163 2000— 1 1 0 0 0 0 0 1 0 1 1 0 0 0 1 1
0xC163 27FF
0 0 1 0 0 Dreg
0xC003 2800— 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1
0xC003 2FFF
0 0 1 0 1 Dreg
Instruction Opcodes
Bin
Dest. src_reg_
half Dreg # 0 Dreg #
Dest. src_reg_
half Dreg # 0 Dreg #
Dest. src_reg_
half Dreg # 0 Dreg #
Dest. src_reg_
half Dreg # 0 Dreg #
Dest. src_reg_
half Dreg # 0 Dreg #
Dest. src_reg_
half Dreg # 0 Dreg #
Dest. src_reg_
half Dreg # 0 Dreg #
src_reg_
1 Dreg #
src_reg_
1 Dreg #
src_reg_
1 Dreg #
src_reg_
1 Dreg #
src_reg_
1 Dreg #
src_reg_
1 Dreg #
src_reg_
1 Dreg #
C-75