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Memory Protection and Properties
Bits
FAULT_DAG
ter (
DCPLB_STATUS
the CPLB-related exception (see
DCPLB Status Register (DCPLB_STATUS)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0xFFE0 0008
FAULT_ILLADDR
0 - No fault
1 - Attempted access to nonexistent memory
FAULT_DAG
0 - Access was made by DAG0
1 - Access was made by DAG1
15 14 13 12 11 10
Figure 6-23. DCPLB Status Register
Bit
FAULT_USERSUPV
to identify the CPLB entry that has triggered the CPLB-related exception
(see
Figure
6-24).
6-62
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
,
FAULT_USERSUPV
) are used to identify the CPLB entry that has triggered
X
X
X
X
X
X
X
X
9
8
0
0
0
0
0
0
0
0
in the ICPLB Status register (
and
in the DCPLB Status regis-
FAULT_RW
Figure
6-23).
X
X
X
X
0
X
X
7
6
5
4
3
2
1
0
0
0
0
0
0
0
ICPLB_STATUS
X
Reset = Undefined
FAULT_RW
0 - Access was read
1 - Access was write
FAULT_USERSUPV
0 - Access was made in User
mode
1 - Access was made in
Supervisor mode
0
0
FAULT[15:0]
Each bit indicates the hit/miss
status of the associated CPLB
entry
) is used
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