Instruction Cache Invalidation - Analog Devices ADSP-BF53x Blackfin Reference

L1 Instruction Memory
• Execute the code of interest. Any cacheable exceptions, such as exit
code, traversed by this code execution are also locked into the
instruction cache.
• Upon exit of the critical code, clear
The critical code (and the instructions which set
locked into Way0.
• Re-enable interrupts, if required.
If all four Ways of the cache are locked, then further allocation into the
cache is prevented.

Instruction Cache Invalidation

The instruction cache can be invalidated by address, cache line, or com-
plete cache. The
based on their line addresses. The target address of the instruction is gen-
erated from the P-registers. Because the instruction cache should not
contain modified (dirty) data, the cache line is simply invalidated, and not
"flushed."
In the following example, the
memory location. If this address has been brought into cache, the corre-
sponding cache line is invalidated after the execution of this instruction.
Example of
ICACHE
iflush [ p2 ] ;
that P2 points to */
Because the
IFLUSH
the memory map and its corresponding cache-line, it is most useful when
the buffer being invalidated is less than the cache size. For more informa-
tion about the
second technique can be used to invalidate larger portions of the cache
directly. This second technique directly invalidates Valid bits by setting
6-18 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
instruction can explicitly invalidate cache lines
IFLUSH
P2
instruction:
/* Invalidate cache line containing address
instruction is used to invalidate a specific address in
instruction, see
IFLUSH
ILOC[3:1]
register contains the address of a valid
Chapter 17, "Cache Control."
and set .
ILOC[0]
) is now
ILOC[0]
A