Rounding Multiplier Results - Analog Devices ADSP-BF53x Blackfin Reference

P SIGN,
8 BITS
31 31 31 31 31 31 31 31
7 6 5 4 3 2 1 0
A0.X
Figure 2-6. Integer Multiplier Results Format

Rounding Multiplier Results

On many multiplier operations, the processor supports multiplier results
rounding (
RND
number by removing a lower order range of bits from that number's repre-
sentation and possibly modifying the remaining portion of the number to
more accurately represent its former value. For example, the original num-
ber will have N bits of precision, whereas the new number will have only
M bits of precision (where N>M). The process of rounding, then, removes
N – M bits of precision from the number.
The bit in the
RND_MOD
provides biased or unbiased rounding. For unbiased rounding, set
bit = 0. For biased rounding, set
For most algorithms, unbiased rounding is preferred.
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 1 1 1 16
option). Rounding is a means of reducing the precision of a
register determines whether the
ASTAT
RND_MOD
Computational Units
MULTIPLIER P OUTPUT
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
A0.W
bit = 1.
option
RND
RND_MOD
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