Analog Devices ADSP-BF53x Blackfin Reference page 952

Instructions Listed By Operation Code
Table C-22. 16-Bit Opcode Instructions (Sheet 13 of 14)
Instruction
and Version
Modify-Increment
Ireg += Mreg (brev)
Store Data Register
[ Ireg ] = Dreg
Store Low Data Register Half
W [ Ireg ] = Dreg_lo
Store High Data Register Half
W [ Ireg ] = Dreg_hi
Add Immediate
Ireg += 2
Subtract Immediate
Ireg –= 2
Add Immediate
Ireg += 4
Subtract Immediate
Ireg –= 4
Store Data Register
[ Ireg ++ Mreg ] = Dreg
Load Data Register
Dreg = [ Preg + uimm6m4 ]
Load Half Word, Zero Extended
Dreg = W [ Preg + uimm5m2 ] (Z)
Load Half Word, Sign Extended
Dreg = W [ Preg + uimm5m2 ] (X)
Load Pointer Register
Preg = [ Preg + uimm6m4 ]
Store Data Register
[ Preg + uimm6m4 ] = Dreg
C-152 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Opcode
Range
0x9EE0—
0x9EEF
0x9F00—
0x9F1F
0x9F20—
0x9F3F
0x9F40—
0x9F5F
0x9F60—
0x9F63
0x9F64—
0x9F67
0x9F68—
0x9F6B
0x9F6C—
0x9F6F
0x9F80—
0x9FFF
0xA000—
0xA3FF
0xA400—
0xA7FF
0xA800—
0xABFF
0xAC00—
0xAFFF
0xB000—
0xB3FF