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Table C-21. Vector Operations Instructions (Sheet 13 of 33)
Instruction
and Version
Vector Multiply
Dreg_even = Dreg_lo_hi * Dreg_lo_hi ,
Dreg_odd = Dreg_lo_hi * Dreg_lo_hi (FU)
Vector Multiply
Dreg_even = Dreg_lo_hi * Dreg_lo_hi ,
Dreg_odd = Dreg_lo_hi * Dreg_lo_hi (IS)
Vector Multiply
Dreg_even = Dreg_lo_hi * Dreg_lo_hi ,
Dreg_odd = Dreg_lo_hi * Dreg_lo_hi (S2RND)
Vector Multiply
Dreg_even = Dreg_lo_hi * Dreg_lo_hi ,
Dreg_odd = Dreg_lo_hi * Dreg_lo_hi (ISS2)
Vector Multiply
Dreg_even = Dreg_lo_hi * Dreg_lo_hi ,
Dreg_odd = Dreg_lo_hi * Dreg_lo_hi (M)
Vector Multiply
Dreg_even = Dreg_lo_hi * Dreg_lo_hi ,
Dreg_odd = Dreg_lo_hi * Dreg_lo_hi (FU, M)
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Opcode
Range
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 0 0 0 1 0 1 0 0 0 1 1 0 0
0xC28C 2000—
0xC28C E7FF
Dreg
half 1 1 0 0
1 1 0 0 0 0 1 1 0 0 0 0 1 1 0 0
0xC30C 2000—
0xC30C E7FF
Dreg
half 1 1 0 0
1 1 0 0 0 0 1 0 0 0 1 0 1 1 0 0
0xC22C 2000—
0xC22C E7FF
Dreg
half 1 1 0 0
1 1 0 0 0 0 1 1 0 0 1 0 1 1 0 0
0xC32C 2000—
0xC32C E7FF
Dreg
half 1 1 0 0
1 1 0 0 0 0 1 0 0 0 0 1 1 1 0 0
0xC21C 2000—
0xC21C E7FF
Dreg
half 1 1 0 0
1 1 0 0 0 0 1 0 1 0 0 1 1 1 0 0
0xC29C 2000—
0xC29C E7FF
Dreg
half 1 1 0 0
Instruction Opcodes
Bin
Dreg
Dest.
src_reg_
half 0
Dreg #
0 Dreg #
Dreg
Dest.
src_reg_
half 0
Dreg #
0 Dreg #
Dreg
Dest.
src_reg_
half 0
Dreg #
0 Dreg #
Dreg
Dest.
src_reg_
half 0
Dreg #
0 Dreg #
Dreg
Dest.
src_reg_
half 0
Dreg #
0 Dreg #
Dreg
Dest.
src_reg_
half 0
Dreg #
0 Dreg #
src_reg_
1 Dreg #
src_reg_
1 Dreg #
src_reg_
1 Dreg #
src_reg_
1 Dreg #
src_reg_
1 Dreg #
src_reg_
1 Dreg #
C-119
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