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L1 Data Memory
A data cache line is in one of three states: invalid, exclusive (valid and
clean), and modified (valid and dirty). If valid data already occupies the
allocated line and the cache is configured for write-back storage, the con-
troller checks the state of the cache line and treats it accordingly:
• If the state of the line is exclusive (clean), the new tag and data
write over the old line.
• If the state of the line is modified (dirty), then the cache contains
the only valid copy of the data.
If the line is dirty, the current contents of the cache are copied back
to external memory before the new data is written to the cache.
The processor provides victim buffers and line fill buffers. These buffers
are used if a cache load miss generates a victim cache line that should be
replaced. The line fill operation goes to external memory. The data cache
performs the line fill request to the system as critical (or requested) word
first, and forwards that data to the waiting DAG as it updates the cache
line. In other words, the cache performs critical word forwarding.
The data cache supports hit-under-a-store miss, and hit-under-a-prefetch
miss. In other words, on a write-miss or execution of a
tion that misses the cache (and is to a cacheable region), the instruction
pipeline incurs a minimum of a 4-cycle stall. Furthermore, a subsequent
load or store instruction can hit in the L1 cache while the line fill
completes.
Interrupts of sufficient priority (relative to the current context) cancel a
stalled load instruction. Consequently, if the load operation misses the L1
Data Memory cache and generates a high latency line fill operation on the
system interface, it is possible to interrupt the core, causing it to begin
processing a different context. The system access to fill the cache line is
not cancelled, and the data cache is updated with the new data before any
further cache miss operations to the respective data bank are serviced. For
more information see
6-34
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
"Exceptions" on page
PREFETCH
4-47.
instruc-
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