Analog Devices ADSP-BF53x Blackfin Reference page 496

Instruction Overview
Table 14-1. Arithmetic Shifts
Syntax
">>>="
">>>", "<<", and
"ASHIFT"
In essence, the magnitude is the power of 2 multiplied by the
number. Positive magnitudes cause multiplication ( N x 2
ative magnitudes produce division ( N x 2
The
dest_reg
sions of the Arithmetic Shift instruction support optional saturation.
See "Saturation" on page 1-17
For 16-bit
src_reg
included. For 32- and 40-bit
through +31, zero included.
The D-register versions of this instruction shift 16 or 32 bits for half-word
and word registers, respectively. The Accumulator versions shift all 40 bits
of those registers.
The D-register versions of this instruction do not implicitly modify the
values. Optionally,
src_reg
. Doing this explicitly modifies the source register.
src_reg
The Accumulator versions always modify the Accumulator source value.
14-10 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Description
The value in dest_reg is right-shifted by the number of places specified
by shift_magnitude. The data size is always 32 bits long. The entire 32
bits of the shift_magnitude determine the shift value. Shift magnitudes
larger than 0x1F result in either 0x00000000 (when the input value is
positive) or 0xFFFFFFFF (when the input value is negative).
Only right shifting is supported in this syntax; there is no equivalent
"<<<=" arithmetic left shift syntax. However, logical left shift is sup-
ported. See the Logical Shift instruction.
The value in src_reg is shifted by the number of places specified in
shift_magnitude, and the result is stored into dest_reg.
The "ASHIFT" versions can shift 32-bit Dreg and 40-bit Accumulator
registers by up to –32 through +31 places.
and can be a 16-, 32-, or 40-bit register. Some ver-
src_reg
for a description of saturation behavior.
, valid shift magnitudes are –16 through +15, zero
src_reg
dest_reg
-n n
or N / 2 ).
, valid shift magnitudes are –32
can be the same D-register as
src_reg
n
) whereas neg-