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Vector Operations Instructions
Table C-21. Vector Operations Instructions (Sheet 10 of 33)
Instruction
and Version
Vector Multiply
Dreg_lo = Dreg_lo_hi * Dreg_lo_hi ,
Dreg_hi = Dreg_lo_hi * Dreg_lo_hi (IS)
Vector Multiply
Dreg_lo = Dreg_lo_hi * Dreg_lo_hi ,
Dreg_hi = Dreg_lo_hi * Dreg_lo_hi (IU)
Vector Multiply
Dreg_lo = Dreg_lo_hi * Dreg_lo_hi ,
Dreg_hi = Dreg_lo_hi * Dreg_lo_hi (T)
Vector Multiply
Dreg_lo = Dreg_lo_hi * Dreg_lo_hi ,
Dreg_hi = Dreg_lo_hi * Dreg_lo_hi (TFU)
Vector Multiply
Dreg_lo = Dreg_lo_hi * Dreg_lo_hi ,
Dreg_hi = Dreg_lo_hi * Dreg_lo_hi (S2RND)
Vector Multiply
Dreg_lo = Dreg_lo_hi * Dreg_lo_hi ,
Dreg_hi = Dreg_lo_hi * Dreg_lo_hi (ISS2)
C-116
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Opcode
Range
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 0 0 0 1 1 0 0 0 0 0 1 0 0
0xC304 2000—
0xC304 E7FF
Dreg
half 1 1 0 0
1 1 0 0 0 0 1 1 1 0 0 0 0 1 0 0
0xC384 2000—
0xC384 E7FF
Dreg
half 1 1 0 0
1 1 0 0 0 0 1 0 0 1 0 0 0 1 0 0
0xC244 2000—
0xC244 E7FF
Dreg
half 1 1 0 0
1 1 0 0 0 0 1 0 1 1 0 0 0 1 0 0
0xC2C4 2000—
0xC2C4 E7FF
Dreg
half 1 1 0 0
1 1 0 0 0 0 1 0 0 0 1 0 0 1 0 0
0xC224 2000—
0xC224 E7FF
Dreg
half 1 1 0 0
1 1 0 0 0 0 1 1 0 0 1 0 0 1 0 0
0xC324 2000—
0xC324 E7FF
Dreg
half 1 1 0 0
Bin
Dreg
Dest.
src_reg_
half 0
Dreg #
0 Dreg #
Dreg
Dest.
src_reg_
half 0
Dreg #
0 Dreg #
Dreg
Dest.
src_reg_
half 0
Dreg #
0 Dreg #
Dreg
Dest.
src_reg_
half 0
Dreg #
0 Dreg #
Dreg
Dest.
src_reg_
half 0
Dreg #
0 Dreg #
Dreg
Dest.
src_reg_
half 0
Dreg #
0 Dreg #
src_reg_
1 Dreg #
src_reg_
1 Dreg #
src_reg_
1 Dreg #
src_reg_
1 Dreg #
src_reg_
1 Dreg #
src_reg_
1 Dreg #
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