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Syntax Terminology
:
,
genreg
R7–0
P5–0
:
,
dagreg
I3–0
M3–0
:
,
sysreg
ASTAT
,
and
LC1
LT0
LT1
USP: The User Stack Pointer Register
:
Dreg
R7–0
:
,
,
Preg
P5–0
SP
:
,
Dreg_even
R0
:
,
Dreg_odd
R1
R3
When combining two moves in the same instruction, the
Dreg_even
register pair, for example from the set
: Optionally
opt_mode
page
9-4).
Instruction Length
In the syntax, comment (a) identifies 16-bit instruction length. Comment
(b) identifies 32-bit instruction length. Comment (c) indicates an instruc-
tion that is not valid on the ADSP-BF535 processor.
Functional Description
The Move Register instruction copies the contents of the source register
into the destination register. The operation does not affect the source reg-
ister contents.
All moves from smaller to larger registers are sign extended.
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
,
,
,
,
SP
FP
A0.X
A0.W
,
,
B3–0
L3–0
,
,
SEQSTAT
SYSCFG
RETI
,
and
,
LB0
LB1
CYCLES
FP
,
,
R2
R4
R6
,
,
R5
R7
and
operands must be members of the same
Dreg_odd
(FU), (S2RND),
,
,
A1.X
A1.W
,
,
,
,
RETX
RETN
RETE
,
, and
CYCLES2
EMUDAT
,
R1:0
R3:2
or
(See
Table 9-1 on
(ISS2)
Move
,
and
RETS
LC0
,
,
.
R5:4
R7:6
9-3
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