Analog Devices ADSP-BF53x Blackfin Reference page 668

Instruction Overview
In the optional reverse source order case (for example, using the (R) syn-
tax), the only difference is the source registers swap places within the
register pair in their byte ordering. Assume a source register pair contains
the data shown in
Table 18-21. I-register Bits and the Byte Alignment
The bytes selected are
Two LSB's of I0 or I1
00b:
01b:
10b:
11b:
The mnemonic derives its name from the fact that the operands are bytes,
the result is two half-words, and the basic arithmetic operation is "plus"
for addition. The single destination register indicates that averaging is
performed.
Flags Affected
None
The ADSP-BF535 processor has fewer
operate differently than subsequent Blackfin family products. For
more information on the ADSP-BF535 status flags, see
on page
Required Mode
User & Supervisor
18-28 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Table 18-21.
src_reg_pair_LO
byte7 byte6
byte6
A-3.
src_reg_pair_HI
byte5 byte4 byte3
byte3
byte4 byte3
byte5 byte4 byte3
byte5 byte4 byte3
flags and some flags
ASTAT
byte2 byte1 byte0
byte2 byte1 byte0
byte2 byte1
byte2
Table A-1