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SEQSTAT Register
The Sequencer Status register (
current state of the sequencer as well as diagnostic information from the
last event.
SEQSTAT
sor mode.
Sequencer Status Register (SEQSTAT)
RO
HWERRCAUSE[1:0]
Holds cause of last hard-
ware error generated by
the core. Hardware errors
trigger interrupt number 5
(IVHW). See
Table
4-10.
SFTRESET
0 - Last core reset was not a
reset triggered by software
1 - Last core reset was a reset
triggered by software, rather
than a hardware powerup reset
Figure 4-11. Sequencer Status Register
Hardware Error Interrupt
The Hardware Error Interrupt indicates a hardware error or system mal-
function. Hardware errors occur when logic external to the core, such as a
memory bus controller, is unable to complete a data transfer (read or
write) and asserts the core's error input signal. Such hardware errors
invoke the Hardware Error Interrupt (interrupt
Table (EVT) and
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
SEQSTAT
is a read-only register and is accessible only in Supervi-
31 30 29 28 27 26
25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
15 14 13 12 11 10
9
8
0
0
0
0
0
0
0
0
,
, and
ILAT
IMASK
Program Sequencer
) contains information about the
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
IVHW
registers). The Hardware Error
IPEND
Reset = 0x0000 0000
0
HWERRCAUSE[4:2]
See description under
bits[1:0], below.
0
0
EXCAUSE[5:0]
Holds information about
the last executed excep-
tion. See
Table
4-11.
in the Event Vector
4-59
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