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Data Watchpoint Address Control Register (WPDACTL)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0xFFE0 7100
X
15 14 13 12 11 10
X
WPDACC1[1:0]
00 - Reserved
01 - Match on write access only
on WPDA1
10 - Match on read access only
on WPDA1
11 - Match on either read or
write accesses on WPDA1
WPDSRC1[1:0]
00 - Reserved
01 - Watch addresses on DAG0
on WPDA1
10 - Watch addresses on DAG1
on WPDA1
11 - Watch addresses on either
DAG0 or DAG1 on WPDA1
WPDACC0[1:0]
00 - Reserved
01 - Match on write access only on WPDA0
or on the WPDA0 to WPDA1 range
10 - Match on read access only on WPDA0
or on the WPDA0 to WPDA1 range
11 - Match on either read or write accesses
on WPDA0 or on the WPDA0 to WPDA1 range
WPDSRC0[1:0]
00 - Reserved
01 - Watch addresses on DAG0 on WPDA0
or on the WPDA0 to WPDA1 range
10 - Watch addresses on DAG1 on WPDA0
or on the WPDA0 to WPDA1 range
11 - Watch addresses on either DAG0 or DAG1
on WPDA0 or on the WPDA0 to WPDA1 range
Figure 21-7. Data Watchpoint Address Control Register
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
X
X
X
X
X
X
X
X
9
8
7
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
6
5
4
3
2
1
0
X
X
X
0
0
X
0
Debug
Reset = Undefined
WPDREN01
0 - Disable range comparison
1 - Enable range comparison:
(Start address = WPDA0,
End address = WPDA1)
WPDRINV01
0 - Inclusive range comparison:
inside the WPDA0 to
WPDA1 range
1 - Exclusive range
comparison: outside the
WPDA0 to WPDA1 range
WPDAEN0
Valid when WPDREN01 = 0
0 - Disable data address
watchpoint, WPDA0
1 - Enable data address
watchpoint, WPDA0
WPDAEN1
Valid when WPDREN01 = 0
0 - Disable data address
watchpoint, WPDA1
1 - Enable data address
watchpoint, WPDA1
WPDCNTEN0
If range comparison is enabled,
this bit enables the counter for
range 01
0 - Disable watchpoint
data address counter 0
1 - Enable watchpoint
data address counter 0
WPDCNTEN1
0 - Disable watchpoint
data address counter 1
1 - Enable watchpoint
data address counter 1
21-13
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