Analog Devices ADSP-BF53x Blackfin Reference page 667

Table 18-19. I-register Bits and the Byte Alignment
The bytes selected are
Two LSB's of I0 or I1
00b:
01b:
10b:
11b:
Options
The Quad 8-Bit Average – Half-Word instruction supports the following
options.
Table 18-20. Options for Quad 8-Bit Average – Half-Word
Option
(RND—)
(T—)
(—L)
(—H)
( ,R)
When used together, the order of the options in the syntax makes no
difference.
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
src_reg_pair_HI
byte7 byte6
byte6
Description
Rounds up the arithmetic mean.
Truncates the arithmetic mean.
Loads the results into the lower byte of each destination half-word.
Loads the results into the higher byte of each destination half-word.
Reverses the order of the source registers within each register pair. Typical
high performance applications cannot afford the overhead of reloading both
register pair operands to maintain byte order for every calculation. Instead,
they alternate and load only one register pair operand each time and alternate
between the forward and reverse byte order versions of this instruction. By
default, the low order bytes come from the low register in the register pair.
The (R) option causes the low order bytes to come from the high register.
Video Pixel Operations
src_reg_pair_LO
byte5 byte4 byte3
byte3
byte4 byte3
byte5 byte4 byte3
byte5 byte4 byte3
byte2 byte1 byte0
byte2 byte1 byte0
byte2 byte1
byte2
18-27