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Table C-17. Arithmetic Operations Instructions (Sheet 25 of 44)
Instruction
and Version
Multiply and Multiply-Accumulate
to Half Register
Dreg_hi = (A1 = Dreg_lo_hi * Dreg_lo_hi) (T)
Multiply and Multiply-Accumulate
to Half Register
Dreg_hi = (A1 = Dreg_lo_hi * Dreg_lo_hi) (TFU)
Multiply and Multiply-Accumulate
to Half Register
Dreg_hi = (A1 = Dreg_lo_hi * Dreg_lo_hi) (S2RND)
Multiply and Multiply-Accumulate
to Half Register
Dreg_hi = (A1 = Dreg_lo_hi * Dreg_lo_hi) (ISS2)
Multiply and Multiply-Accumulate
to Half Register
Dreg_hi = (A1 = Dreg_lo_hi * Dreg_lo_hi) (IH)
Multiply and Multiply-Accumulate
to Half Register
Dreg_hi = (A1 = Dreg_lo_hi * Dreg_lo_hi) (M)
Multiply and Multiply-Accumulate
to Half Register
Dreg_hi = (A1 = Dreg_lo_hi * Dreg_lo_hi) (FU, M)
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Opcode Range
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0xC044 1800—
1 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0
0xC044 D9FF
Dreg
half
0xC0C4 1800—
1 1 0 0 0 0 0 0 1 1 0 0 0 1 0 0
0xC0C4 D9FF
Dreg
half
0xC024 1800—
1 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0
0xC024 D9FF
Dreg
half
0xC124 1800—
1 1 0 0 0 0 0 1 0 0 1 0 0 1 0 0
0xC124 D9FF
Dreg
half
0xC164 1800—
1 1 0 0 0 0 0 1 0 1 1 0 0 1 0 0
0xC164 D9FF
Dreg
half
0xC014 1800—
1 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0
0xC014 D9FF
Dreg
half
0xC094 1800—
1 1 0 0 0 0 0 0 1 0 0 1 0 1 0 0
0xC094 D9FF
Dreg
half
Instruction Opcodes
Bin
0 1 1 0 0 Dest.
Dreg #
0 1 1 0 0 Dest.
Dreg #
0 1 1 0 0 Dest.
Dreg #
0 1 1 0 0 Dest.
Dreg #
0 1 1 0 0 Dest.
Dreg #
0 1 1 0 0 Dest.
Dreg #
0 1 1 0 0 Dest.
Dreg #
src_reg_
src_reg_
0 Dreg #
1 Dreg #
src_reg_
src_reg_
0 Dreg #
1 Dreg #
src_reg_
src_reg_
0 Dreg #
1 Dreg #
src_reg_
src_reg_
0 Dreg #
1 Dreg #
src_reg_
src_reg_
0 Dreg #
1 Dreg #
src_reg_
src_reg_
0 Dreg #
1 Dreg #
src_reg_
src_reg_
0 Dreg #
1 Dreg #
C-79
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