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devices, such as peripheral data FIFOs, reads are destructive. Each time
the device is read, the FIFO advances, and the data cannot be recovered
and re-read.
When accessing off-chip memory-mapped devices that have state
dependencies on the number of read operations on a given address
location, disable interrupts before performing the load operation.
On-chip peripherals are protected against this issue.
Working With Memory
This section contains information about alignment of data in memory and
memory operations that support semaphores between tasks. It also con-
tains a brief discussion of MMR registers and a core MMR programming
example.
Alignment
Nonaligned memory operations are not directly supported. A nonaligned
memory reference generates a Misaligned Access exception event (see
"Exceptions" on page
8-bit video data) can properly be nonaligned in memory, alignment excep-
tions may be disabled by using the
some instructions in the quad 8-bit group automatically disable alignment
exceptions.
Cache Coherency
For shared data, software must provide cache coherency support as
required. To accomplish this, use the
Control Instructions" on page
through the core MMRs (see
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
4-47). However, because some datastreams (such as
DISALGNEXCPT
FLUSH
6-37), and/or explicit line invalidation
"Data Test Registers" on page
instruction. Moreover,
instruction (see
"Data Cache
6-38).
Memory
6-71
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