Analog Devices ADSP-BF53x Blackfin Reference page 891

Table C-17. Arithmetic Operations Instructions (Sheet 37 of 44)
Instruction
and Version
Multiply and Multiply-Accumulate
to Data Register
Dreg_odd = (A1 += Dreg_lo_hi * Dreg_lo_hi) (ISS2)
Multiply and Multiply-Accumulate
to Data Register
Dreg_odd = (A1 += Dreg_lo_hi * Dreg_lo_hi) (M)
Multiply and Multiply-Accumulate
to Data Register
Dreg_odd = (A1 += Dreg_lo_hi * Dreg_lo_hi) (FU, M)
Multiply and Multiply-Accumulate
to Data Register
Dreg_odd = (A1 += Dreg_lo_hi * Dreg_lo_hi) (IS, M)
Multiply and Multiply-Accumulate
to Data Register
Dreg_odd = (A1 += Dreg_lo_hi * Dreg_lo_hi) (S2RND, M)
Multiply and Multiply-Accumulate
to Data Register
NOTE: When issuing compatible load/store instructions in parallel with a Multiply and Multiply-Accumu-
late instruction, add 0x0800 0000 to the Multiply and Multiply-Accumulate opcode.
Dreg_odd = (A1 += Dreg_lo_hi * Dreg_lo_hi) (ISS2, M)
Multiply and Multiply-Accumulate
to Data Register
Dreg_odd = (A1 – = Dreg_lo_hi * Dreg_lo_hi)
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Opcode Range 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0xC129 1800— 1 1 0 0 0 0 0 1 0 0 1 0 1 0 0 1
0xC129 D9FF
Dreg
half
0xC019 1800— 1 1 0 0 0 0 0 0 0 0 0 1 1 0 0 1
0xC019 D9FF
Dreg
half
0xC099 1800— 1 1 0 0 0 0 0 0 1 0 0 1 1 0 0 1
0xC099 D9FF
Dreg
half
0xC119 1800— 1 1 0 0 0 0 0 1 0 0 0 1 1 0 0 1
0xC119 D9FF
Dreg
half
0xC039 1800— 1 1 0 0 0 0 0 0 0 0 1 1 1 0 0 1
0xC039 D9FF
Dreg
half
0xC139 1800— 1 1 0 0 0 0 0 1 0 0 1 1 1 0 0 1
0xC139 D9FF
Dreg
half
0xC00A 1800— 1 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0
0xC00A D9FF
Dreg
half
Instruction Opcodes
Bin
0 1 1 0 0 Dest.
Dreg #
0 1 1 0 0 Dest.
Dreg #
0 1 1 0 0 Dest.
Dreg #
0 1 1 0 0 Dest.
Dreg #
0 1 1 0 0 Dest.
Dreg #
0 1 1 0 0 Dest.
Dreg #
0 1 1 0 0 Dest.
Dreg #
src_reg_ src_reg_
0 Dreg # 1 Dreg #
src_reg_ src_reg_
0 Dreg # 1 Dreg #
src_reg_ src_reg_
0 Dreg # 1 Dreg #
src_reg_ src_reg_
0 Dreg # 1 Dreg #
src_reg_ src_reg_
0 Dreg # 1 Dreg #
src_reg_ src_reg_
0 Dreg # 1 Dreg #
src_reg_ src_reg_
0 Dreg # 1 Dreg #
C-91