Analog Devices ADSP-BF53x Blackfin Reference page 905

Table C-20. Video Pixel Operations Instructions (Sheet 4 of 5)
Instruction
and Version
Quad 8-Bit Average-Half Word
Dreg = BYTEOP2P (Dreg_pair, Dreg_pair) (TH)
Quad 8-Bit Average-Half Word
Dreg = BYTEOP2P (Dreg_pair, Dreg_pair) (RNDL, R)
Quad 8-Bit Average-Half Word
Dreg = BYTEOP2P (Dreg_pair, Dreg_pair) (RNDH, R)
Quad 8-Bit Average-Half Word
Dreg = BYTEOP2P (Dreg_pair, Dreg_pair) (TL, R)
Quad 8-Bit Average-Half Word
NOTE: When issuing compatible load/store instructions in parallel with a Quad 8-Bit Average-Half
Word instruction, add 0x0800 0000 to the Quad 8-Bit Average-Half Word opcode.
Dreg = BYTEOP2P (Dreg_pair, Dreg_pair) (TH, R)
Quad 8-Bit Pack
NOTE: When issuing compatible load/store instructions in parallel with a Quad 8-Bit Pack instruction,
add 0x0800 0000 to the Quad 8-Bit Pack opcode.
Dreg = BYTEPACK (Dreg, Dreg)
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Opcode
Range 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0xC436 4000— 1 1 0 0 0 1 0 x x x 1 1 0 1 1 0
0xC436 6E3F
0 1 0 0 Dest.
0xC416 2000— 1 1 0 0 0 1 0 x x x 0 1 0 1 1 0
0xC416 2E3F
0 0 1 0 Dest.
0xC436 2000— 1 1 0 0 0 1 0 x x x 1 1 0 1 1 0
0xC436 2E3F
0 0 1 0 Dest.
0xC416 6000— 1 1 0 0 0 1 0 x x x 0 1 0 1 1 0
0xC416 7E3F
0 1 1 0 Dest.
0xC436 6000— 1 1 0 0 0 1 0 x x x 1 1 0 1 1 0
0xC436 7E3F
0 1 1 0 Dest.
0xC418 0000— 1 1 0 0 0 1 0 x x x 0 1 1 0 0 0
0xC418 0E3F
0 0 0 0 Dest.
Instruction Opcodes
Bin
0 0 0 Source 0
Dreg # Dreg #
0 0 0 Source 0
Dreg # Dreg #
0 0 0 Source 0
Dreg # Dreg #
0 0 0 Source 0
Dreg # Dreg #
0 0 0 Source 0
Dreg # Dreg #
0 0 0 Source 0
Dreg # Dreg #
Source 1
Dreg #
Source 1
Dreg #
Source 1
Dreg #
Source 1
Dreg #
Source 1
Dreg #
Source 1
Dreg #
C-105