Analog Devices ADSP-BF53x Blackfin Reference page 523

The instruction supports only biased rounding. The
register has no bearing on the rounding behavior of this instruction.
ASTAT
See "Rounding and Truncating" on page 1-19
ing behavior.
Flags Affected
The following flags are affected by this instruction:
• is set if result is zero; cleared if nonzero.
AZ
• is set if result is negative; cleared if non-negative.
AN
• is cleared.
V
All other flags are unaffected.
Required Mode
User & Supervisor
Parallel Issue
This instruction can be issued in parallel with specific other 16-bit
instructions. For details, see
Example
r1.l = r6+r7(rnd20) ;
r1.l = r6-r7(rnd20) ;
r1.h = r6+r7(rnd20) ;
r1.h = r6-r7(rnd20) ;
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
"Issuing Parallel Instructions" on page
Arithmetic Operations
bit in the
RND_MOD
for a description of round-
20-1.
15-11