Analog Devices ADSP-BF53x Blackfin Reference page 372

Instruction Overview
Parallel Issue
This instruction can be issued in parallel with specific other instructions.
For more information, see "Issuing Parallel Instructions" on page 20-1.
Example
w[ i1 ] = r3.h ;
w[ i3 ++ ] = r7.h ;
w[ i0 -- ] = r1.h ;
w[ p4 ] = r2.h ;
w[ p2 ++ p0 ] = r5.h ;
Also See
Store Low Data Register Half
Special Applications
To write consecutive, aligned 16-bit values for high-performance DSP
operations, use the Store Data Register instructions instead of these
Half-Word instructions. The Half-Word Store instructions use only half
the available 32-bit data bus bandwidth, possibly imposing a bottleneck
constriction in the data flow rate.
8-48 ADSP-BF53x/BF56x Blackfin Processor Programming Reference