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Register Files
Three separate buses (two load, one store) connect the Register File to the
L1 data memory, each bus being 32 bits wide. Transfers between the Data
Register File and the data memory can move up to two 32-bit words of
valid data in each cycle. Often, these represent four 16-bit words.
Accumulator Registers
In addition to the Data Register File, the processor has two dedicated,
40-bit accumulator registers, called
its 16-bit low half (
(
). Each can also be referred to as a 32-bit register (
An.X
the lower 32 bits, or as a complete 40-bit result register (
These examples illustrate this convention:
A0 = A1;
/* 40-bit move */
A1.W = R7;
/* 32-bit move */
A0.H = R5.H; /* 16-bit move */
R6.H = A0.X; /* read 8-bit value and sign extend to 16 bits */
39
39
32
A0.X
39
32
A0.X
Figure 2-4. 40-Bit Accumulator Registers
2-8
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
) or high half (
An.L
A0
31
A0.W
31
16 15
A0.H
A0.L
and
. Each can be referred to as
A0
A1
) plus its 8-bit extension
An.H
0
39
A1
0
39
32
31
A1.X
A1.W
0
39
32
31
16
15
A1.X
A1.H
) consisting of
An.W
).
An
0
0
0
A1.L
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