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L1 Data Memory
• If
DCBS = 1
With
DCBS = 1
caches, each a 2-Way set associative 16K byte cache. Each Bank
serves an alternating set of 8M byte blocks of memory.
For example, Data Bank B caches all data accesses for the first 8M
byte of memory address range. That is, every 8M byte of range vies
for the two line entries (rather than every 16K byte repeat). Like-
wise, Data Bank A caches data located above 8M byte and below
16M byte.
For example, if the application is working from a data set that is
1M byte long and located entirely in the first 8M byte of memory,
it is effectively served by only half the cache, that is, by Data Bank
B (a 2-Way set associative 16K byte cache). In this instance, the
application never derives any benefit from Data Bank A.
For most applications, it is best to operate with
However, if the application is working from two data sets, located in two
memory spaces at least 8M byte apart, closer control over how the cache
maps to the data is possible. For example, if the program is doing a series
of dual MAC operations in which both DAGs are accessing data on every
cycle, by placing DAG0's data set in one block of memory and DAG1's
data set in the other, the system can ensure that:
• DAG0 gets its data from Data Bank A for all of its accesses and
• DAG1 gets its data from Data Bank B.
This arrangement causes the core to use both data buses for cache line
transfer and achieves the maximum data bandwidth between the cache
and the core.
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ADSP-BF53x/BF56x Blackfin Processor Programming Reference
,
selects Data Bank A instead of Data Bank B.
A[23]
, the system functions more like two independent
.
DCBS = 0
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