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Arithmetic Operations Instructions
Table C-17. Arithmetic Operations Instructions (Sheet 18 of 44)
Instruction
and Version
Multiply and Multiply-Accumulate
to Accumulator
NOTE: When issuing compatible load/store instructions in parallel with a Multiply and Multiply-Accumu-
late instruction, add 0x0800 0000 to the Multiply and Multiply-Accumulate opcode.
A1 = Dreg_lo_hi * Dreg_lo_hi (W32, M)
Multiply and Multiply-Accumulate
to Accumulator
A1 += Dreg_lo_hi * Dreg_lo_hi
Multiply and Multiply-Accumulate
to Accumulator
A1 += Dreg_lo_hi * Dreg_lo_hi (FU)
Multiply and Multiply-Accumulate
to Accumulator
A1 += Dreg_lo_hi * Dreg_lo_hi (IS)
Multiply and Multiply-Accumulate
to Accumulator
A1 += Dreg_lo_hi * Dreg_lo_hi (W32)
Multiply and Multiply-Accumulate
to Accumulator
A1 += Dreg_lo_hi * Dreg_lo_hi (M)
C-72
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Opcode Range
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0xC070 1800—
1 1 0 0 0 0 0 0 0 1 1 1 0 0 0 0
0xC070 D83F
Dreg
half
0xC001 1800—
1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1
0xC001 D83F
Dreg
half
0xC081 1800—
1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1
0xC081 D83F
Dreg
half
0xC101 1800—
1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 1
0xC101 D83F
Dreg
half
0xC061 1800—
1 1 0 0 0 0 0 0 0 1 1 0 0 0 0 1
0xC061 D83F
Dreg
half
0xC011 1800—
1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1
0xC011 D83F
Dreg
half
Bin
0 1 1 0 0 0 0 0 src_reg_
0 1 1 0 0 0 0 0 src_reg_
0 1 1 0 0 0 0 0 src_reg_
0 1 1 0 0 0 0 0 src_reg_
0 1 1 0 0 0 0 0 src_reg_
0 1 1 0 0 0 0 0 src_reg_
src_reg_
0 Dreg #
1 Dreg #
src_reg_
0 Dreg #
1 Dreg #
src_reg_
0 Dreg #
1 Dreg #
src_reg_
0 Dreg #
1 Dreg #
src_reg_
0 Dreg #
1 Dreg #
src_reg_
0 Dreg #
1 Dreg #
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