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Instruction Overview
The first instruction provides a bit-wise XOR of
. The resulting intermediate bit is XOR'ed with the
A1
of the operation is left-shifted into the least significant bit of
the operation. This operation is illustrated in
not modified by this operation.
+
CC
A1[39]
A1[38]
A0[39]
After Operation
A0[38]
A0[37]
Figure 12-4. XOR of A0 AND A1, Left-Shifted into LSB of A0
The second instruction in this class performs a bit-wise XOR of
cally AND'ed with
flag. The result of the operation is placed into both the
CC
least significant bit of the destination register.
This operation is illustrated in
The Accumulator
of
are overwritten with zero, and dr[0] = IN.
dreg_lo
12-14
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
+
+
A1[37]
A0[38]
A0[37]
A0[36]
A0[39:0]
. The resulting intermediate bit is XOR'ed with the
A1
Figure
is not modified by this operation. The upper 15 bits
A0
logically AND'ed with
A0
CC
Figure
12-4. The
+
A1[0]
IN
A0[0]
IN
12-5.
flag. The result
following
A0
bit is
CC
Left Shift by 1
Following XOR
Reduction
logi-
A0
flag and the
CC
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