Functional Units - Analog Devices ADSP-BF53x Blackfin Reference

Glossary
Table 1-1. Registers (Cont'd)
Register Description
Loop Count LC0 and LC1; contains 32-bit counter of the zero overhead loop executions.
Loop Bottom LB0 and LB1; contains 32-bit address of the bottom of a zero overhead loop.
Index The set of 32-bit registers I0, I1, I2, I3 that normally contain byte addresses of
Register data structures. Abbreviated I-register or Ireg.
Modify The set of 32-bit registers M0, M1, M2, M3 that normally contain offset values
Registers that are added or subtracted to one of the Index Registers. Abbreviated as Mreg.
Length The set of 32-bit registers L0, L1, L2, L3 that normally contain the length (in
Registers bytes) of the circular buffer. Abbreviated as Lreg. Clear Lreg to disable circular
addressing for the corresponding Ireg. Example: Clear L3 to disable circular
addressing for I3.
Base The set of 32-bit registers B0, B1, B2, B3 that normally contain the base address
Registers (in bytes) of the circular buffer. Abbreviated as Breg.

Functional Units

The architecture includes the three processor sections shown in
Table 1-2. Processor Sections
Processor
Data Address
Generator (DAG)
Multiply and
Accumulate Unit
(MAC)
Arithmetic Logical
Unit (ALU)
1-14 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Description
Calculates the effective address for indirect and indexed memory
accesses. Consists of two sections–DAG0 and DAG1.
Performs the arithmetic functions on data. Consists of two sections
(MAC0 and MAC1)–each associated with an Accumulator (A0 and A1,
respectively).
Performs arithmetic computations and binary shifts on data. Operates
on the Data Registers and Accumulators. Consists of two units (ALU0
and ALU1), each associated with an Accumulator (A0 and A1, respec-
tively). Each ALU operates in conjunction with a Multiply and Accu-
mulate Unit.
Table 1-2.