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Instruction Overview
Functional Description
The Load Pointer Register instruction loads a 32-bit P-register with a
32-bit word from an address specified by a P-register.
The indirect address and offset must yield an even multiple of 4 to main-
tain 4-byte word address alignment. Failure to maintain proper alignment
causes a misaligned memory access exception.
Options
The Load Pointer Register instruction supports the following options.
• Post-increment the source pointer by 4 bytes.
• Post-decrement the source pointer by 4 bytes.
• Offset the source pointer with a small (6-bit), word-aligned (multi-
ple of 4), unsigned constant.
• Offset the source pointer with a large (18-bit), word-aligned (mul-
tiple of 4), signed constant.
• Frame Pointer (
(multiple of 4), negative constant.
The indexed
FP
subroutine or function. Positive offsets relative to
arguments from a called function) can be accomplished using one of the
other versions of this instruction. Preg includes the Frame Pointer and
Stack Pointer.
Auto-increment or auto-decrement pointer registers cannot also be the
destination of a Load instruction. For example,
instruction because it prescribes two competing values for the Stack
Pointer–the data returned from memory, and post-incremented
Similarly,
P0=[P0++]
causes an undefined instruction exception.
8-8
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
) relative and offset with a 7-bit, word-aligned
FP
-relative form is typically used to access local variables in a
and
P1=[P1++]
(useful to access
FP
sp=[sp++]
, etc. are invalid. Such an instruction
is not a valid
.
SP++
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