Cache Write Method; Iprio Register And Write Buffer Depth - Analog Devices ADSP-BF53x Blackfin Reference

Cache Write Method

Cache write memory operations can be implemented by using either a
write-through method or a write-back method:
• For each store operation, write-through caches initiate a write to
external memory immediately upon the write to cache.
If the cache line is replaced or explicitly flushed by software, the
contents of the cache line are invalidated rather than written back
to external memory.
• A write-back cache does not write to external memory until the line
is replaced by a load operation that needs the line.
The L1 Data Memory employs a full cache line width copyback buffer on
each data bank. In addition, a two-entry write buffer in the L1 Data
Memory accepts all stores with cache inhibited or store-through protec-
tion. An
SSYNC

IPRIO Register and Write Buffer Depth

The Interrupt Priority register (
the write buffer on Port A (see
6-28).
The
IPRIO[3:0]
rupt watermark. When an interrupt occurs, causing the processor to
vector from a low priority interrupt service routine to a high priority inter-
rupt service routine, the size of the write buffer increases from two to eight
32-bit words deep. This allows the interrupt service routine to run and
post writes without an initial stall, in the case where the write buffer was
already filled in the low priority interrupt routine. This is most useful
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
instruction flushes the write buffer.
IPRIO
"L1 Data Memory Architecture" on page
bits can be programmed to reflect the low priority inter-
) can be used to control the size of
Memory
6-35