Analog Devices ADSP-BF53x Blackfin Reference page 650

Instruction Overview
The Dual 16-Bit Add / Clip instruction provides byte alignment directly
in the source register pairs
ters and .
I0 I1
• The two LSBs of the
source register pair
• The two LSBs of the
source register pair
The relationship between the I-register bits and the byte alignment is
illustrated in Table
In the default source order case (for example, not the ( – , R) syntax),
assuming a source register pair contains the following.
Table 18-5. I-register Bits and the Byte Alignment
The bytes selected are
Two LSB's of I0 or I1
00b:
01b:
10b:
11b:
This instruction prevents exceptions that would otherwise be caused by
misaligned 32-bit memory loads issued in parallel.
Options
The ( – , R) syntax reverses the order of the source registers within each
register pair. Typical high performance applications cannot afford the
overhead of reloading both register pair operands to maintain byte order
for every calculation. Instead, they alternate and load only one register
pair operand each time and alternate between the forward and reverse byte
18-10 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
and
src_reg_0
register determine the byte alignment for
I0
(typically
src_reg_0
register determine the byte alignment for
I1
(typically
src_reg_1
18-5.
src_reg_pair_HI
byte7 byte6 byte5
byte5
byte6 byte5
based on index regis-
src_reg_1
).
R1:0
).
R3:2
src_reg_pair_LO
byte4 byte3 byte2
byte3 byte2
byte4 byte3 byte2
byte4 byte3 byte2
byte4 byte3
byte1 byte0
byte1 byte0
byte1