Analog Devices ADSP-BF53x Blackfin Reference page 101

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ADSP-BF53x/BF56x Blackfin Processor Programming Reference
If multiplying and accumulating to a half register:
When copying the lower 16 bits to the destination
half register, the Accumulator contents are scaled. If
scaling produces a signed value greater than 16 bits,
the number is saturated to its maximum positive or
negative value.
This option indicates integer multiplication with
high half word extraction. The Accumulator is satu-
rated at 32 bits, and bits [31:16] of the
Accumulator are rounded, and then copied into the
destination half register.
Input data operands are signed fraction with no
extension bits in the Accumulators at 32 bits.
Left-shift correction of the product is performed, as
required. This option is used for legacy GSM
speech vocoder algorithms written for 32-bit Accu-
mulators. For this option only, this special case
applies:
0x8000 x 0x8000 = 0x7FFF
Operation uses mixed-multiply mode. Valid only
for MAC1 versions of the instruction. Multiplies a
signed fraction by an unsigned fractional operand
with no left-shift correction. Operand one is signed;
operand two is unsigned. MAC0 performs an
unmixed multiply on signed fractions by default, or
another format as specified. That is, MAC0 exe-
cutes the specified signed/signed or unsigned/
unsigned multiplication. The (
used alone or in conjunction with one other format
option.
Computational Units
.
) option can be
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