Analog Devices ADSP-BF53x Blackfin Reference page 906

Video Pixel Operations Instructions
Table C-20. Video Pixel Operations Instructions (Sheet 5 of 5)
Instruction
and Version
Quad 8-Bit Subtract
(Dreg, Dreg) = BYTEOP16M (Dreg_pair, Dreg_pair)
Quad 8-Bit Subtract
NOTE: When issuing compatible load/store instructions in parallel with a Quad 8-Bit Subtract instruc-
tion, add 0x0800 0000 to the Quad 8-Bit Subtract opcode.
(Dreg, Dreg) = BYTEOP16M (Dreg_pair, Dreg_pair) (R)
Quad 8-Bit Subtract-Abso-
lute-Accumulate
SAA (Dreg_pair, Dreg_pair)
Quad 8-Bit Subtract-Abso-
lute-Accumulate
NOTE: When issuing compatible load/store instructions in parallel with a Quad 8-Bit Subtract-Abso-
lute-Accumulate instruction, add 0x0800 0000 to the Quad 8-Bit Subtract-Absolute-Accumulate
opcode.
SAA (Dreg_pair, Dreg_pair) (R)
Quad 8-Bit Unpack
(Dreg, Dreg) = BYTEUNPACK Dreg_pair
Quad 8-Bit Unpack
NOTE: When issuing compatible load/store instructions in parallel with a Quad 8-Bit Unpack instruc-
tion, add 0x0800 0000 to the Quad 8-Bit Unpack opcode.
(Dreg, Dreg) = BYTEUNPACK Dreg_pair (R)
C-106 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Opcode
Range 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0xC415 4000— 1 1 0 0 0 1 0 x x x 0 1 0 1 0 1
0xC415 4FFF
0 1 0 0 Dest. 1
0xC415 6000— 1 1 0 0 0 1 0 x x x 0 1 0 1 0 1
0xC415 6FFF
0 1 1 0 Dest. 1
0xC412 0000— 1 1 0 0 0 1 0 x x x 0 1 0 0 1 0
0xC412 003F
0 0 0 0 0 0 0 0 0 0 Source 0
0xC412 2000— 1 1 0 0 0 1 0 x x x 0 1 0 0 1 0
0xC412 203F
0 0 1 0 0 0 0 0 0 0 Source 0
0xC418 4000— 1 1 0 0 0 1 0 x x x 0 1 1 0 0 0
0xC418 4FF8
0 1 0 0 Dest. 1
0xC418 6000— 1 1 0 0 0 1 0 x x x 0 1 1 0 0 0
0xC418 6FF8
0 1 1 0 Dest. 1
Bin
Dest. 0 Source 0
Dreg # Dreg # Dreg #
Dest. 0 Source 0
Dreg # Dreg # Dreg #
Dreg #
Dreg #
Dest. 0 Source 0
Dreg # Dreg # Dreg #
Dest. 0 Source 0
Dreg # Dreg # Dreg #
Source 1
Dreg #
Source 1
Dreg #
Source 1
Dreg #
Source 1
Dreg #
0 0 0
0 0 0