Analog Devices ADSP-BF53x Blackfin Reference page 164

Events and Interrupts
An interrupt is an event that changes normal processor instruction flow
and is asynchronous to program flow. In contrast, an exception is a soft-
ware initiated event whose effects are synchronous to program flow.
The event system is nested and prioritized. Consequently, several service
routines may be active at any time, and a low priority event may be
pre-empted by one of higher priority.
The processor employs a two-level event control mechanism. The proces-
sor System Interrupt Controller (SIC) works with the Core Event
Controller (CEC) to prioritize and control all system interrupts. The SIC
provides mapping between the many peripheral interrupt sources and the
prioritized general-purpose interrupt inputs of the core. This mapping is
programmable, and individual interrupt sources can be masked in the
SIC.
The CEC supports nine general-purpose interrupts (
addition to the dedicated interrupt and exception events that are described
in Table 4-7. It is recommended that the two lowest priority interrupts
( and
IVG14 IVG15
seven prioritized interrupt inputs (
Refer to the product data sheet for the default system interrupt mapping.
Table 4-7. Core Event Mapping
Core Events
4-30 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
) be reserved for software interrupt handlers, leaving
IVG7
Event Source
Emulation (highest priority)
Reset
NMI
Exception
Reserved
Hardware Error
Core Timer
–
IVG7
– ) to support the system.
IVG13
) in
IVG15
Core Event
Name
EMU
RST
NMI
EVX
–
IVHW
IVTMR