Hardware Errors And Exception Handling - Analog Devices ADSP-BF53x Blackfin Reference

Hardware Errors and Exception Handling

Note the interrupt service routine must reside in L1 cache or SRAM mem-
ory and must not generate a cache miss, an L2 memory access, or a
peripheral access, as the processor is already busy completing the original
cache line fill operation. If a load or store operation is executed in the
interrupt service routine requiring one of these accesses, then the interrupt
service routine is held off while the original external access is completed,
before initiating the new load or store.
If the interrupt service routine finishes execution before the load operation
has completed, then the processor continues to stall, waiting for the fill to
complete.
This same behavior is also exhibited for stalls involving reads of slow data
memory or peripherals.
Writes to slow memory generally do not show this behavior, as the writes
are deemed to be single cycle, being immediately transferred to the write
buffer for subsequent execution.
For detailed information about cache and memory structures, see
6, "Memory."
Hardware Errors and Exception Handling
The following sections describe hardware errors and exception handling.
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