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ICPLB Status Register (ICPLB_STATUS)
0xFFE0 1008
FAULT_ILLADDR
0 - No fault
1 - Attempted access to nonexistent memory
Figure 6-24. ICPLB Status Register
DCPLB_FAULT_ADDR and ICPLB_FAULT_ADDR
Registers
The DCPLB Address register (
Address register (
fault in the L1 Data Memory or L1 Instruction Memory, respectively. See
Figure 6-25
and
The
DCPLB_FAULT_ADDR
only while in the faulting exception service routine.
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
X
X
X
X
X
X
X
X
15 14 13 12 11 10
9
8
0
0
0
0
0
0
0
0
DCPLB_FAULT_ADDR
ICPLB_FAULT_ADDR
Figure
6-26.
and
X
X
X
X
0
X
X
X
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
) and ICPLB Fault
) hold the address that has caused a
ICPLB_FAULT_ADDR
Memory
Reset = Undefined
FAULT_USERSUPV
0 - Access was made in User
mode
1 - Access was made in
Supervisor mode
FAULT[15:0]
Each bit indicates hit/miss
status of associated CPLB
entry
registers are valid
6-63
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