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Table C-17. Arithmetic Operations Instructions (Sheet 31 of 44)
Instruction
and Version
Multiply and Multiply-Accumulate
to Half Register
Dreg_hi = (A1 – = Dreg_lo_hi * Dreg_lo_hi) (FU, M)
Multiply and Multiply-Accumulate
to Half Register
Dreg_hi = (A1 – = Dreg_lo_hi * Dreg_lo_hi) (IS, M)
Multiply and Multiply-Accumulate
to Half Register
Dreg_hi = (A1 – = Dreg_lo_hi * Dreg_lo_hi) (IU, M)
Multiply and Multiply-Accumulate
to Half Register
Dreg_hi = (A1 – = Dreg_lo_hi * Dreg_lo_hi) (T, M)
Multiply and Multiply-Accumulate
to Half Register
Dreg_hi = (A1 – = Dreg_lo_hi * Dreg_lo_hi) (TFU, M)
Multiply and Multiply-Accumulate
to Half Register
Dreg_hi = (A1 – = Dreg_lo_hi * Dreg_lo_hi) (S2RND, M)
Multiply and Multiply-Accumulate
to Half Register
Dreg_hi = (A1 – = Dreg_lo_hi * Dreg_lo_hi) (ISS2, M)
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Opcode Range
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0xC096 1800—
1 1 0 0 0 0 0 0 1 0 0 1 0 1 1 0
0xC096 D9FF
Dreg
half
0xC116 1800—
1 1 0 0 0 0 0 1 0 0 0 1 0 1 1 0
0xC116 D9FF
Dreg
half
0xC196 1800—
1 1 0 0 0 0 0 1 1 0 0 1 0 1 1 0
0xC196 D9FF
Dreg
half
0xC056 1800—
1 1 0 0 0 0 0 0 0 1 0 1 0 1 1 0
0xC056 D9FF
Dreg
half
0xC0D6 1800—
1 1 0 0 0 0 0 0 1 1 0 1 0 1 1 0
0xC0D6 D9FF
Dreg
half
0xC036 1800—
1 1 0 0 0 0 0 0 0 0 1 1 0 1 1 0
0xC036 D9FF
Dreg
half
0xC136 1800—
1 1 0 0 0 0 0 1 0 0 1 1 0 1 1 0
0xC136 D9FF
Dreg
half
Instruction Opcodes
Bin
0 1 1 0 0 Dest.
Dreg #
0 1 1 0 0 Dest.
Dreg #
0 1 1 0 0 Dest.
Dreg #
0 1 1 0 0 Dest.
Dreg #
0 1 1 0 0 Dest.
Dreg #
0 1 1 0 0 Dest.
Dreg #
0 1 1 0 0 Dest.
Dreg #
src_reg_
src_reg_
0 Dreg #
1 Dreg #
src_reg_
src_reg_
0 Dreg #
1 Dreg #
src_reg_
src_reg_
0 Dreg #
1 Dreg #
src_reg_
src_reg_
0 Dreg #
1 Dreg #
src_reg_
src_reg_
0 Dreg #
1 Dreg #
src_reg_
src_reg_
0 Dreg #
1 Dreg #
src_reg_
src_reg_
0 Dreg #
1 Dreg #
C-85
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