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Events and Interrupts
Core Interrupt Latch Register (ILAT)
Reset value for bit 0 is emulator-dependent. For all bits, 0 - Interrupt not latched, 1 - Interrupt latched
31 30 29 28 27 26
0xFFE0 210C
IVG15
IVG14
IVG13
IVG12
IVG11
IVG10
IVG9
Figure 4-6. Core Interrupt Latch Register
IPEND Register
The Core Interrupt Pending register
nested interrupts (see
responding interrupt is currently active or nested at some level. It may be
read in Supervisor mode, but not written. The
Event Controller to temporarily disable interrupts on entry and exit to an
interrupt service routine.
When an event is processed, the corresponding bit in
least significant bit in
that is currently being serviced. At any given time,
status of all nested events.
4-40
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
15 14 13 12 11 10
9
8
0
0
0
0
0
0
0
0
Figure
4-7). Each bit in
that is currently set indicates the interrupt
IPEND
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
X
) keeps track of all currently
(IPEND
indicates that the cor-
IPEND
IPEND[4]
IPEND
Reset = 0x0000 000X
EMU (Emulation) - RO
RST (Reset) - RO
NMI (Nonmaskable Interrupt) - RO
EVX (Exception) - RO
IVHW (Hardware Error)
IVTMR (Core Timer)
IVG7
IVG8
bit is used by the
is set. The
IPEND
holds the current
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