Analog Devices ADSP-BF53x Blackfin Reference page 1016

Index
FLUSHINV (data cache line flush and
invalidate) instruction, 6-37, 17-7,
C-101
force emulation (EMUEXCPT)
instruction, 16-11,
force exception (EXCPT) instruction,
16-20, C-99
force interrupt / reset (RAISE) instruction,
3-11, 16-17, C-99
foregnd_reg bit field deposit instruction,
13-10
FP (frame pointer). See frame pointer (FP)
register
fractional
data format, D-1
mode, 2-15, D-6
representation, 2-5
fractional multiplier results format,
fractions
binal point, 1-16
binary convention, 1-16
multiplication, 2-45
frame pointer (FP) register, 1-13, 4-6, 5-6,
8-8, 8-12, 8-38, 10-17,
fully associative, definition,
functions, exponent detection,
G
general-purpose interrupt
RAISE instruction, 4-47
SIC, 4-30
with multiple peripheral interrupts,
genreg, syntax, 9-3
global enabling and disabling interrupts,
4-48
global interrupt disable bit,
GSM (global system for mobile
communications)
speech-compression routines,
speech vocoder algorithms,
I-14 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
C-99
2-17
C-2
6-75
2-48
4-37
4-41
2-23
2-41
H
hardware
loops, 4-21
reset, 3-12, 3-13
hardware error
core event, 4-30
core event mapping,
interrupt (HWE), 4-59,
multiple, 4-60
Harvard architecture, 1-4,
hierarchical memory structure,
high half-word Accumulator extraction
with saturation and rounding (IH)
multiply and multiply-accumulate to
half-register instruction,
high half-word accumulator extraction with
saturation and rounding (IH)
multiply 16-bit operands instruction,
15-43
use with instructions,
HWE (hardware error interrupt), 4-59,
4-60
HWERRCAUSE (hardware error cause)
field, 4-59
I
IAR (interrupt assignment register),
ICACHE instruction, 6-18
ICPLB address (ICPLB_ADDRx) registers,
6-47, 6-60
ICPLB_ADDRx (ICPLB address) registers,
6-47, 6-60
ICPLB data (ICPLB_DATAx) registers,
6-47, 6-55
ICPLB_DATAx (ICPLB data) registers,
6-47, 6-55
ICPLB fault address
(ICPLB_FAULT_ADDR) register,
6-63
4-30
4-60
6-3
1-4
15-58
15-58
1-8