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Load/Store Operation
This ordering provides significant performance advantages in the opera-
tion of most memory instructions. However, it can cause side effects that
the programmer must be aware of to avoid improper system operation.
When writing to or reading from nonmemory locations such as off-chip
I/O device registers, the order of how read and write operations complete
is often significant. For example, a read of a status register may depend on
a write to a control register. If the address is the same, the read would
return a value from the store buffer rather than from the actual I/O device
register, and the order of the read and write at the register may be
reversed. Both these effects could cause undesirable side effects in the
intended operation of the program and peripheral. To ensure that these
effects do not occur in code that requires precise (strong) ordering of load
and store operations, synchronization instructions (
should be used.
Synchronizing Instructions
When strong ordering of loads and stores is required, as may be the case
for sequential writes to an I/O device for setup and control, use the core or
system synchronization instructions,
The
instruction ensures all pending core operations have completed
CSYNC
and the store buffer (between the processor core and the L1 memories) has
been flushed before proceeding to the next instruction. Pending core oper-
ations may include any pending interrupts, speculative states (such as
branch predictions), or exceptions.
Consider the following example code sequence:
IF CC JUMP away_from_here;
CSYNC;
R0 = [P0];
away_from_here:
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ADSP-BF53x/BF56x Blackfin Processor Programming Reference
CSYNC
or
, respectively.
CSYNC
SSYNC
or
)
SSYNC
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